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rs_trigger support #248
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rs_trigger support #248
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| } | ||
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| if (aloads.size() > 1) { | ||
| if (aloads.size() > 2) { |
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Please update the diagnostic text for "more than two unsupported"
| for (auto driven_chunk2 : dffsr_q.chunks()) { | ||
| for (auto [named_chunk, name] : generate_subfield_names(driven_chunk2, type)) { | ||
| auto set = netlist.Mux(RTLIL::SigSpec(0, named_chunk.bitwidth()), | ||
| RTLIL::SigSpec(-1, named_chunk.bitwidth()), aloads[1].trigger); |
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I think this assumes the clear always comes before the reset. Consider e.g.
always @(negedge CLK or posedge A or posedge B) begin
if (A)
Q <= 8'b1111_0000;
else if (B)
Q <= 8'b0000_1111;
else
Q <= D1;
end
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Is it naming problem only?
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It's not. I think for the above example the set and clear signals will be inferred the wrong way for some of the bits. Also we need to arrange if both A and B are high, then A takes precedence. I'm not sure how Yosys deals with it
| @@ -0,0 +1,88 @@ | |||
| read_slang <<EOF | |||
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Test needs to be added to CMakeLists
Closes #169
yosys-slang produces error message "multiple asynchronous loads unsupported" for following construction(always block with clock plus two asynchronous signals):
but native yosys's read_verilog does not, and generates
$dffsrcell.The fix allows such construction and issues
$dffsrcell call producing rtlil