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@alexeyvoh alexeyvoh commented Nov 13, 2025

Closes #169
yosys-slang produces error message "multiple asynchronous loads unsupported" for following construction(always block with clock plus two asynchronous signals):

always @(negedge CLK or negedge RST or posedge SET) begin
    if (~RST)
      Q <= 8'b0000_0000;
    else if (SET)
      Q <= 8'b1111_1111;
    else
      Q <= D1;
  end

but native yosys's read_verilog does not, and generates $dffsr cell.
The fix allows such construction and issues $dffsr cell call producing rtlil

  cell $dffsr $driver$Q
    parameter \CLK_POLARITY 0
    parameter \SET_POLARITY 1
    parameter \CLR_POLARITY 0
    parameter \WIDTH 8
    connect \CLK \CLK
    connect \SET $5y
    connect \CLR $6y
    connect \D \D1
    connect \Q \Q
  end
  cell $mux $5
    parameter \WIDTH 8
    connect \A 8'00000000
    connect \B 8'11111111
    connect \S \SET
    connect \Y $5y
  end
  cell $mux $6
    parameter \WIDTH 8
    connect \A 8'00000000
    connect \B 8'11111111
    connect \S \RST
    connect \Y $6y
  end

@codecov

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}

if (aloads.size() > 1) {
if (aloads.size() > 2) {
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Please update the diagnostic text for "more than two unsupported"

for (auto driven_chunk2 : dffsr_q.chunks()) {
for (auto [named_chunk, name] : generate_subfield_names(driven_chunk2, type)) {
auto set = netlist.Mux(RTLIL::SigSpec(0, named_chunk.bitwidth()),
RTLIL::SigSpec(-1, named_chunk.bitwidth()), aloads[1].trigger);
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I think this assumes the clear always comes before the reset. Consider e.g.

  always @(negedge CLK or posedge A or posedge B) begin
    if (A)
      Q <= 8'b1111_0000;
    else if (B)
      Q <= 8'b0000_1111;
    else
      Q <= D1;
  end

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Is it naming problem only?

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It's not. I think for the above example the set and clear signals will be inferred the wrong way for some of the bits. Also we need to arrange if both A and B are high, then A takes precedence. I'm not sure how Yosys deals with it

@@ -0,0 +1,88 @@
read_slang <<EOF
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Test needs to be added to CMakeLists

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Support for SR latches and SR FFs

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